1. Field of the Invention
This invention concerns an integrated circuit used in a high speed semiconductor memory in which noise or voltage fluctuation occurs during the reading operation. More particularly, this invention concerns an improvement of an input buffer circuit and an output circuit of an integrated circuit which eliminates the influence of the noise associated with the output circuit on the input buffer circuit which eliminates the influence of the noise associated with the output circuit on the input buffer circuit.
2. Description of the Prior Art
Generally, an integrated circuit is formed in a semiconductor chip, and electrically connected to inner leads provides in a package by bonding wires. Those bonding wires have some resistance and inductance. Thus, a voltage drop occurs due to the resistance, and a counterelectromotive force is generated due to the inductance in response to an operating current.
FIG. 1 is a diagram of a conventional integrated circuit which includes an input buffer circuit and an output circuit used in a memory device. Semiconductor integrated circuit chip 3 comprises an input buffer circuit 1 and an output buffer circuit 2.
The input buffer circuit 1 is a CMOS Schmitt trigger type, and includes N type MOS transistors T3, T4 and T5, and a P type MOS transistor T2. The gate electrodes of the transistors T3, T4 and T5 are connected to a bonding pad 5 formed on the chip. The source electrode of the transistor T2 is supplied with a power source voltage VDD, and the source electrode of the transistor T5 is connected to a bonding pad 4 formed on the chip through a wiring 200 supplied with a reference voltage VSS. An output of the CMOS Schmitt trigger circuit, namely a connection of the drain electrodes of the transistors T2 and T3 is connected to the input of an inverter circuit 6. An output Ain of the inverter circuit 6 is used as, e.g., an address signal or a clock signal, and has the same phase and same level with respect to the input signal A. A resistance RS and a parasitic capacitance CS exist between the bonding pad 5 and the input buffer circuit 1.
Reference I/O and I/O represents data buses formed in the chip, and are connected to a memory circuit (not shown) and also are connected to a control circuit 7 of the output buffer circuit 2. T1 and T7 are drive transistors, and are supplied with an output of the control circuit 7 at the respective gate electrodes thereof. An output, namely a conection of the drive transistors T7 and T1, is connected to a load capacitor CL through an output node N3. A ground level 100 is located at external of the integrated circuit. The bonding pad 4 is connected to a lead pin N4 on the package by a bonding wire having an inductance l and a resistance r. LEX shows an inductance which exists in an external wiring between the lead in N4 and ground level 100.
In this circuit, at the read-out of a data "0", the charge stored in the load capacitor CL is rapidly discharged to ground through the drive transistor T1, the wiring 200, the resistance r, and the inductance l and LEX. This discharge causes a noise or rapid voltage fluctuation. Namely, to read out the data "0", the potential level of the gate electrode of the drive transistor T1 becomes high, and the transistor T1 switches to an ON state. In this state, a discharging current Iout flows to ground and causes an increase of potential level at pad 4 due to the voltage drop at the resistor and the product of the dIout/dt and the inductance of (l+LEX) with respect to the ground level.
Signal A is an input signal from external of the chip supplied by an input signal supplying circuit (not shown) of low output impedance. Thus, signal A is only slightly influenced, if at all, by the noise or the fluctuation of the reference voltage VSS. Therefore, the gate to source voltage Vgs of transistor T5 fluctuates due to the fluctuation of the reference voltage VSS which appears on the source electrode of transistor T5.
The relationship between the operating signals is illustrated in FIG. 2. In FIG. 2, VS represents a reference voltage which appears at rhe source electrode of the transistor T5. N2, N3 and Ain represent operating signals at the gate electrode of the transistor T1, at the node N3 and the output of the inverter 6, respectively. Due to the rise of the reference voltage VSS, the potential of the input signal A drops, relatively. Thus, the gate to source voltage VGS may go lower than the logical low leverl VIL (the level to cause transistor T2 of the input buffer circuit to be conductive) of the input buffer circuit. When the gate to source voltage VGS becomes lower than the logical low level VIL, the level of the signal Ain becomes a low level, and an undesirable fluctuation 11 occurs. This fluctuation sometimes causes an error in operation of the memory device. To remove the fluctuation, it is necessary to set the logical high level VIH (the level to cause transistors T3 and T5 of the input buffer circuit to be conductive) sufficiently high. However, by setting the VIH high, the margin for the VIH is decreased.